IEEE 2010 Projects,B.E, M.E, VLSI Proj, VHDL, Verilog training - Chennai

Posted On: Aug-21-10 22:42

Digital Data Labs(DDL) is an Indian company located in Chennai, the IT gateway of South India. DDL employees have more than 20 years of combined experience in the design and development of FPGA design, Board design and Embedded system design for the corporate, students and research community. We guide IEEE paper based B.E / B.Tech., M.E / M.Tech., Projects. We actively update our base of knowledge to keep pace with the latest trends in today's accelerating change in technology. This responsibility to meet researchers ever growing requirements has proven to be the key to our success. We use the latest design tools, VHDL/Verilog for digital designs, SPICE for analog designs and DSP technology for imaging and control optimization.


CHENNAI – 600 044, Ph: 044 - 22418063, Cell: 9487091315,



IEEE Transactions on Very Large Scale Integration (VLSI) Systems –2010

1. An Adaptively Pipelined Mixed Synchronous-Asynchronous Digital FIR Filter Chip Operating at 1.3 Gigahertz

2. Complexity Analysis and Efficient Implementations of Bit Parallel Finite Field Multipliers Based on Karatsuba-Ofman Algorithm on FPGAs

3. An Antiharmonic, Programmable, DLL-Based Frequency Multiplier for Dynamic Frequency Scaling

4. New Architectural Design of CA-Based Codec

5. A Memory-Efficient and Highly Parallel Architecture for Variable Block Size Integer Motion Estimation in H.264/AVC

6. Design of a Scalable and Programmable Sound Synthesizer

7. Bandwidth Adaptive Hardware Architecture of K-Means Clustering for Video Analysis

8. A Novel Architecture for Block Interleaving Algorithm in MB-OFDM Using Mixed Radix System

9. A Reverse-Encoding-Based On-Chip Bus Tracer for Efficient Circular-Buffer Utilization

10. Dynamic Bit-Width Adaptation in DCT: An Approach to Trade Off Image Quality and Computation Energy

11. Design Space Exploration of Hard-Decision Viterbi Decoding: Algorithm and VLSI Implementation

12. An Efficient 4-D 8PSK TCM Decoder Architecture

13. Implementation of a Self-Motivated Arbitration Scheme for the Multilayer AHB Busmatrix

14. Interframe Bus Encoding Technique and Architecture for MPEG-4 AVC/H.264 Video Compression

15. A Multibank Memory-Based VLSI Architecture of DVB Symbol Deinterleaver

16. VLSI Implementation of BCH Error Correction for Multilevel Cell NAND Flash Memory

17. Low Complexity Digit Serial Systolic Montgomery Multipliers for Special Class of {rm GF}(2^{m})

18. Single- and Multi-core Configurable AES Architectures for Flexible Security

19. An Efficient Multimode Multiplier Supporting AES and Fundamental Operations of Public-Key Cryptosystems

20. Improving FPGA Performance for Carry-Save Arithmetic

21. A High-Performance Three-Engine Architecture for H.264/AVC Fractional Motion Estimation

22. A Low-Cost VLSI Implementation for Efficient Removal of Impulse Noise

23. Design of High-Throughput Fully Parallel LDPC Decoders Based on Wire Partitioning

24. Compressive Acquisition CMOS Image Sensor: From the Algorithm to Hardware Implementation

25. Optimal Sigma Delta Modulator Architectures for Fractional- {N} Frequency Synthesis

26. A New VLSI Architecture of Parallel Multiplier–Accumulator Based on Radix-2 Modified Booth Algorithm

27. A VLSI Architecture and Algorithm for Lucas–Kanade-Based Optical Flow Computation

28. Design and Analysis of High-Throughput Lossless Image Compression Engine Using VLSI-Oriented FELICS Algorithm

29. Low-Complexity Switch Network for Reconfigurable LDPC Decoders


1. Capacity-aware linear MMSE detector for OFDM-SDMA systems

2. Unified scaling factor approach for turbo decoding algorithms

3. Improved channel access protocol for cooperative ad hoc networks

4. Blind carrier frequency offset estimator for multi-input multi-output-orthogonal frequency division multiplexing systems over frequency-selective fading channels

5. Low-complexity joint data detection and channel equalisation for highly mobile orthogonal frequency division multiplexing systems

Any other projects suggested by the Students/Staffs, based on published IEEE papers can also be undertaken.

Abstract of the above mentioned projects will be sent on request by mail.

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